Up to 3 × I 2C interfaces (SMBus/PMBus).Up to 168 I/O ports with interrupt capability.

Up to 17 timers: up to twelve 16-bit and two 32-bit timers up to 180 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input.General-purpose DMA: 16-stream DMA controller with FIFOs and burst support.3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode.V BAT supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM.32 kHz oscillator for RTC with calibration.Internal 16 MHz factory-trimmed RC (1% accuracy).1.7 V to 3.6 V application supply and I/Os.Chrom-ART Accelerator™ for enhanced graphic content creation (DMA2D).LCD-TFT controller with fully programmable resolution (total width up to 4096 pixels, total height up to 2048 lines and pixel clock up to 83 MHz).LCD parallel interface, 8080/6800 modes.Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, Compact Flash/NOR/NAND memories.Up to 256+4 KB of SRAM including 64-KB of CCM (core coupled memory) data RAM.Up to 2 MB of Flash memory organized into two banks allowing read-while-write.Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions.

St nucleo higher adc resolution